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NXP Semiconductors /NeoM3 /QEI /IE

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Interpret as IE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INX_INT)INX_INT 0 (TIM_INT)TIM_INT 0 (VELC_INT)VELC_INT 0 (DIR_INT)DIR_INT 0 (ERR_INT)ERR_INT 0 (ENCLK_INT)ENCLK_INT 0 (POS0_INT)POS0_INT 0 (POS1_INT)POS1_INT 0 (POS2_INT)POS2_INT 0 (REV0_INT)REV0_INT 0 (POS0REV_INT)POS0REV_INT 0 (POS1REV_INT)POS1REV_INT 0 (POS2REV_INT)POS2REV_INT 0 (REV1_INT)REV1_INT 0 (REV2_INT)REV2_INT 0 (MAXPOS_INT)MAXPOS_INT 0RESERVED

Description

Interrupt enable register

Fields

INX_INT

When 1, the INX_Int interrupt is enabled.
TIM_INT

When 1, the TIN_Int interrupt is enabled.
VELC_INT

When 1, the VELC_Int interrupt is enabled.
DIR_INT

When 1, the DIR_Int interrupt is enabled.
ERR_INT

When 1, the ERR_Int interrupt is enabled.
ENCLK_INT

When 1, the ENCLK_Int interrupt is enabled.
POS0_INT

When 1, the POS0_Int interrupt is enabled.
POS1_INT

When 1, the POS1_Int interrupt is enabled.
POS2_INT

When 1, the POS2_Int interrupt is enabled.
REV0_INT

When 1, the REV0_Int interrupt is enabled.
POS0REV_INT

When 1, the POS0REV_Int interrupt is enabled.
POS1REV_INT

When 1, the POS1REV_Int interrupt is enabled.
POS2REV_INT

When 1, the POS2REV_Int interrupt is enabled.
REV1_INT

When 1, the REV1_Int interrupt is enabled.
REV2_INT

When 1, the REV2_Int interrupt is enabled.
MAXPOS_INT

When 1, the MAXPOS_Int interrupt is enabled.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data